1. Field of Invention
The present invention relates to a semiconductor structure. More particularly, the present invention relates to an electrostatic discharge (ESD) protection circuit using a floating salicide.
2. Description of Related Art
In the fabrication of an integrated circuit (IC) device, such as dynamic random access memory (DRAM) or statistic random access memory (SRAM), ESD is one of the main factors causing IC damage. For example, when one walks on a carpet with semiconductor wafers, if relative humidity (RH) is high, an electrostatic voltage of about a few hundred volts may exist on one's body and wafers. If the RH is very low, the electrostatic voltage may be even as high as about a few thousand volts. If a conductive object occasionally contacts the wafers, a strong ESD could occur and damage the ICs on the wafers. In order to solve the ESD problem, typically an ESD protection circuit branches out at a place between an internal circuit and input/output (I/O) pads. The ESD protection circuit usually is formed by an on-chip manner.
Moreover, since the thickness of the gate oxide in a semiconductor device is greatly reduced as integration goes high. This causes that a break voltage of the gate oxide is approaching to a junction breakdown voltage of source/drain junction or even is lower. In this situation, the capability of the ESD protection circuit is largely degraded. In addition, the internal circuit is usually designed according to a minimum design rule without proper design for resisting a large transient current induced by the ESD process. The addition design to resist ESD usually needs sufficient space at, for example, the rim from a contact to a diffusion region or the rim from a contact to a gate electrode. As a result, the ESD effect easily causes a damage to the device as the integration is greatly reduced. The ESD effect becomes one of the main problems causing device defect in the submicron semiconductor fabrication. It is important to reduce the ESD effect for the semiconductor manufacturers.
FIG 1A and FIG. 1B are two circuits, schematically illustrating two conventional ESD protection circuits. In FIG. 1A, electrostatic charges flow to an internal circuit 10 through an input port (INP). The electrostatic charges can be absorbed by a ground Vss through an N-type metal-oxide semiconductor (MOS) transistor N1 before the charges enter the internal circuit 10. The internal circuit 10 is thereby protected from the electrostatic charges. The N-type MOS transistor perform as a conventional ESD protection circuit. In FIG. 1B, the electrostatic charges also flow to the internal circuit 10 but have been absorbed another ESD protection circuit, which includes an N-type MOS transistor (NMOS) N1 and a P-type MOS (PMOS) transistor P1. The NMOS transistor N1 is coupled to a ground source Vss, and the PMOS transistor P1 is coupled to a system voltage source V.sub.DD. As a result, the transistors N1 and P1 work together as the ESD protection circuit to protect the internal circuit 10 from ESD effect.
FIG. 2 is a cross-sectional view, schematically illustrating the ESD protection circuit with respect to FIG. 1. FIG. 3 is a top view, schematically the ESD protection circuit with respect to FIG. 1, in which the cross-sectional view of FIG. 2 is taken along the cross-sectional line I-I'. In FIG. 2, the NMOS transistor N1 is formed on a semiconductor substrate 20. The NMOS transistor N1 includes a drain region 22, a source region 24, a gate oxide layer 25 on the substrate 20, and a gate electrode 26 on the gate oxide 25. There is an insulating layer 28 formed over the substrate 20 to cover the NMOS transistor N1. A contact 30 is formed in the insulating layer 28 to have coupling with the drain region 22, and a contact 32 is formed in the insulating layer 28 to have coupling with the source region 24. The opposite end of the contact 30 is coupled to an I/O pad, and the opposite end of the contact 32 is coupled to a ground source Vss.
In FIG. 3, the contacts 30, 32 are shown with a circular structure on the source region 24. The drain region 22 is located between two adjacent source regions 24 but with a separation by the gate electrodes 26, which are also coupled together. The source region 24 and the gate electrode 26 are coupled to the ground source Vss, and the drain region 22 is coupled the I/O line. The ESD transient current I.sub.1 is directed to the ground source 26 from the contact 30 in the drain region 22.
However, in this conventional design, if the transient current is nonuniformly turned-on, or there are defects in the structure, such as the point defect 34, the transient current I.sub.1 is easily crowding at the weak ESD turn-on point and the point defect 34. As the transient current I.sub.1 is trapped to the point defect 34, it causes a local high temperature and results in a damage to the integrated circuit device. In this situation, the ESD protection circuit largely loses its protecting function.